Marvell招聘IC工程师
全球领先的芯片设计厂商Marvell开启校园招聘啦~
大量前端，DFT, 验证等岗位
需要内推的童鞋可以
发送简历到邮箱taozhang3260@163.com
咨询：微信公众号或者邮箱留言
一定要注明投递岗位和期望城市
此文长期有效~~
Responsibility:
Write RTL code for Low power and multi-clock domain designs.
Perform synthesis and pre- and post-layout timing closure.
Run the whole front-end design flow such as Synthesis, power analysis, and Formal check etc.
Contribute test specifications and support evaluation of the design in coordination with application and product engineering.
Provide design documentation, descriptions and information to application engineers, field application engineers, prodsuct engineers, and customers.
Requirement:
Major in EE, CS or related, Master Degree
Familiar with Verilog and RTL design
Good problem solving and communication skills
Good written and spoken English. Be able to work together with global team.
Familiar with System-Verilog and UVM verification methodology is a plus
Familiar with script languages(perl,tcl,sh etc.) is a plus
Familiar with STA timing flow is a plus
Job Description:
This is a system level position, with the combination skills of hardware, software, FPGA and all the EE/CS relevant knowledge, candidates with software/hardware/FPGA background are all welcomed, the working content including but not limited to the following items:
IP/Chip level verification
Validation framework architect
Networking standard research and test suite development
Hardware emulator (Palladium/Veloce) development
Software (debug tool, product driver, windows/linux application) development
Test suite execution, including function coverage points and regression
Global team co-work
Qualification:
BSEE/MSEE Experience with validation/application on semiconductor products, or design/development on data-communication systems
Need to have solid knowledge with Ethernet based Networking/Automotive technology
Need to have thorough understanding with general electrical engineering principles, like basic electronic circuit design, basic logic design communication theory, high speed board design, signal integrity etc
Knowledge with Ethernet PHY devices, L2/L3 switches, NIC cards, or embedded systems, test and measurement, test automation, script, etc. is highly appreciated
Clear logical analysis ability and debug skill
Must be willing to work in a multi-tasking, fast pace, team oriented working environment
Must have valid verbal and oral communication skill in English and Chinese language
Job Responsibilities:
This position is for the staff verification engineer. This headcount will supplement our read channel team in Shanghai and work on our future read channel project to guarantee our tapeout schedule and department success
Work together with algorithm team and design team to develop testplan and testcases for various blocks in our Read Channel products.
Maintain and help improve UVM based verification environment.
Develop checker/driver and test cases to verify read channel designs.
Research on some advanced verification technology such as assertion based formal verification.
Requirements:
Major in EE, CS or related, master’s degree
Familiar with Verilog and RTL design
Familiar with System-Verilog and UVM verification methodology
Familiar with script languages (perl,tcl,sh etc.) is a plus
Familiar with digital signal processing knowledge is a plus
Good problem solving and communication skills
Good written and spoken English. Be able to work together with global team.
This is an entry level, hardware engineering oriented system engineer position. The engineer will be part of the vertical system engineering team composed with hardware engineering, software engineering, firmware engineering, FPGA design engineering, signal integrity engineering, and others. The IC products to work with include Automotive/Networking Ethernet PHY/NIC/Switch/SoC, high speed SerDes based PHYs, DTV front end components, PLC PHYs, and so on. System engineering team is responsible for many post silicon engineering efforts like product validation, platform development, collateral development, technical support and so on.
Job Responsibilities:
- Schematic design.
- PCB Layout review.
- Product validation using various lab. instruments in an automated test environment.
- Technical support to customers.
- Debug and improve the products.
- BS/MS in EE.
- Must have good knowledge with basic electronic circuit/logic design and data communication theories/systems.
- Must be willing to work in a multi-tasking, fast pace, team oriented working environment.
- Must be able to quickly absorb different kinds of knowledge and apply them in the works.
- Must have strong verbal and oral communication skill.
- Working experience on board level hardware design, logic/FPGA design, or software development are preferred.
- Working experience on test and measurement is highly appreciated.
- Familiarity with Ethernet and network protocols are some pluses.
FPGA Engineer
Description
Work with global architecture and designers to get a full deep insight on the IC products(Optical/Copper/Automotive PHY, Switch products)
FPGA logic design is developing FPGA/Emulator based IP regarding cutting-edge Ethernet Protocol(IEEE802.3/IEEE802.1)
FPGA verificaiton design is resonpible for IC prototyping, pre-silicon & post-silicon validation
FPGA hardware designe develops for Hardware tools, schematic design and PCB layout
Design integral system tool development, research and complete architecture level products
Qualifications
MS in EE or related.
Must have solid knowledge and skill with Verilog/SystemVerilog logic design
Skilled in FPGA tools is preferred
Skilled in UVM/VMM is a plus
Familiar with schematic and PCB layout is a plus
Familiar with Emulator(Palladium/Veloce) is a plus
Must have good knowledge with basic electronic circuit design.
Must be willing to work in a multi-tasking, fast pace, team oriented working environment
Must be able to quickly absorb different kinds of knowledge and apply them in the works
Working experience on logic/FPGA design, board level hardware design, or software development are preferred
DFT design engineer
Specific Responsibilities:
1. DFT plan definition, implementation, and signoff the DFT design;2. Finish the DFT design, including: test architecture definition, MBIST insertion, Memory repair, Scan chain insertion & compression, On chip clocking for at-speed test, boundary scan chain insertion, test structure verification;3. Provide test mode SDC to implementation team and support the SoC test mode timing closure;4. DFT pattern generation and simulation. Fault coverage analysis and improve;5. Support DFT pattern bring up on ATE and provide support of failure diagnose and yield improving.
Required Qualifications:
1. Master's Degree in Electrical or Computer Engineering required;2. Familiar with the Mentor or Synopsys tool flow;3. Confident with Verilog and / or VHDL;4. Good English/communication skills and willingness to work with a global team;5. Good learning competency and be able to work in diverse areas in a flexible environment
Requirements:
Bachelor’s degree in Computer Science, Electrical Engineering or related fields and 3-5 years of related professional experience.
Master’s degree and/or PhD in Computer Science, Electrical Engineering or related fields with 2-3 years of experience.
Good understanding of popular operating systems such as Windows, Linux, Mac OS
Familiar with programming using one or more language: C/C++, Python, Shell. Python is a MUST.
Experience in firmware testing or development, storage related working experience is a plus.
Knowledge of mass storage interface, such as NVMe is a plus
Familiar with protocol analyzer/tools, knowledge of protocol trace analysis is a plus.
Willingness to take on challenges and learn new technologies
Solid Verbal and written English communication skills.
Ability to work within a team environment as well as ability to work independently.
Self motivated, conscientious, patient, clear headed and hardworking.
Job Description:
Our product includes analog chip and mixed-signal chip used in hard disk drive, we do tests on internal platform and customer’s platform. We need to understand the product and provide guidelines to improve the performance. Solve customer’s problems and support internal investigation are our responsibilities
In this position, you need to know how to use lab equipment to measure signals, can make plan and write scripts to complete data collection, you need good sense to analyze data and provide conclusion
Qualification:
Typically requires a Master’s degree in EE, Communication or related fields
Need knowledge in analog and digital electronics
Know Matlab / Python is required
Familiar with lab equipment is preferred
Would be better if has data analysis experience
Become a member of a worldclass analog design team in providing high performance analog and mixed mode circuits and IPs for leading data communications and networking products. Designers have opportunities to design high performance Serdes, analog-to-digital converters (ADC), digital-to-analog converters (DAC), filter, adaptive equalizers, clock and data recovery (CDR) circuits, and phase locked loop (PLL) or other timing circuits. Team members participate in circuit architecture, circuit implementation, design review, layout, and silicon validation.
◇ Solid understanding on circuit analysis, verification and IC design technology
◇ Experience using analog simulation tools .
◇ Good silicon debug capability .
◇ Ability to work effectively within a team environment
- Responsible for Key IP development, including design, guiding layout, debug.
- Responsible for working closely with marketing, application, product and test engineers
- Responsible for bench evaluation in Lab for the designed silicon
- Responsible for coaching the layout engineer
- Responsible for mix-signal processing products design
Other analog design experiences in one or more of the following fields are highly desired:
◇ precision band gap, low noise high precision opamp, precision comparator, switch-capacitor circuit;
◇ Serdes, PLLs, oscillators.
◇ delta-sigma ADC, SAR ADC or other high speed ADC.
Hardware application engineer
Responsible for board/chip level silicon validation/characterization on Marvell’s internal IPs such as High-Speed SerDes, DDR, PLL, ADC etc.
Responsible for script development (knowledge of Python, C++, Matlab, Excel VBA is a plus) of automate testing.
Provides IP bring up/debugging support to SoC teams.
Provides IP usage training to Marvell’s internal FAE.
Work with IP design team on new chip features, definitions, and bring-up.
Work with architecture team on future product definitions.
Develop technical collateral such as application notes, user guides, data sheet and test reports.
Qualification：
MS in EE/CE or equivalent.
Good fundamental knowledge in analog/digital circuit and data communication system.
Working experience or knowledge in any of the following SerDes technologies is preferred – SATA/SAS, PCI Express, USB etc.
Working experience or knowledge on semiconductor chip lab testing and measurement.
Must be willing to work in a multi-tasking, fast pace, and team oriented working environment.
Good communication skills in English and capable of independent work with less guidance.
New graduate or 1~2 years of related industry experience.
Layout engineer
Be a part of the Central Analog Layout Team at Marvell chinaMain responsibility is perform analog layout and related drc/lvs verification, debug and fix violations
Will be responsible for all levels of analog/mixed-signal layout from block level to AFE top level integration and physical verification
Qualification：BS degree of electronic engineering, computer scienceBe familiar in high frequency analog/mixed-signal layout methodsBe familiar with 16/12/7nm technology, experience in 5nm is preferredBe familiar with cadence virtuoso, synopsys laker and calibre drc/lvsGood communication skills in written and verbal EnglishGood team work and communication skills. Hardworking and self-motivated under a high competition IP teamGood understanding of layout impact on device matching, noise coupling from signal, supply and substrateGood understanding the importance of signal flow, power/ground structure and block placement in layout floorplanBe familiar with SKILL/Perl/TCL program is preferred
内推简历请戳邮箱：taozhang3260@163.com
一定要注明投递岗位和期望城市
往期回顾
IC工程师：百万年薪路上的20个阶段，你在哪个阶段？
静态时序分析STA合集一
静态时序分析ＳＴＡ合集二
时序基本概念介绍<sdc合集>
数字后端基本概念合集（一）
数字后端基本概念合集（二）
数字后端基本概念合集（三）
Low Power概念介绍合集
数字后端dbGet使用方法合集
号外，数字后端交流群招人啦
IC圈的世界杯 | 论芯片设计的胜利十一人
知否？知否？Block PD应该提交哪些数据？
Timing ECO手修攻略
数字后端面试100问（2019全新版）
数字后端面试100问（校招版）
简历请戳邮箱：taozhang3260@163.com
觉得有用的话，给我点个好看吧
