1、型号：

https://www.intel.cn/content/dam/altera-www/global/zh_CN/pdfs/literature/hb/stratix-10/s10-overview-ch.pdf

Then you can manually modify the DEVICE in QSF file to 1SG10M chip as below.

set_global_assignment -name DEVICE 1SG10MHN3F74C2LG_U1 or: set_global_assignment -name DEVICE 1SG10MHN3F74C2LG_U2

2、资源概述：

LVDS:

https://www.intel.cn/content/dam/altera-www/global/zh_CN/pdfs/literature/hb/stratix-10/ug-s10-lvds-ch.pdf

https://www.intel.com/content/www/us/en/programmable/documentation/sam1439794388346.html

https://www.intel.cn/content/www/cn/zh/programmable/documentation/mcn1441092958198.html#mcn1441781431631

收发器:

IO:

https://www.intel.cn/content/www/cn/zh/programmable/documentation/sam1438349166154.html

PLL:

https://www.intel.cn/content/dam/altera-www/global/zh_CN/pdfs/literature/hb/stratix-10/ug-s10-clkpll-ch.pdf

MEM:

LAB:

pinout:

https://www.intel.cn/content/dam/www/programmable/us/en/pdfs/literature/dp/stratix-10/pcg-01020.pdf

JTAG:

配置：

https://www.intel.cn/content/dam/altera-www/global/zh_CN/pdfs/literature/hb/stratix-10/ug-s10-config-ch.pdf

参考：

https://baijiahao.baidu.com/s?id=1649509682926754886&wfr=spider&for=pc

https://www.intel.cn/content/www/cn/zh/programmable/support/support-resources/design-guidance/fpga-developer/stratix-10.html

https://www.intel.cn/content/dam/altera-www/global/en_US/support/boards-kits/stratix10/si_gx/s10gx_si_d.pdf

https://www.intel.com/content/www/us/en/programmable/products/stratix-series/s10/support/documentation.html

引脚表格搜索：

Pin Information for the Intel® Stratix®10 1SG10M Device

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/dp/stratix-10/1sg10m.pdf?wapkw=Pin%20Information%20for%20the%20Intel%C2%AE%20Stratix%C2%AE10%201SG10M%20Device

https://www.intel.com/content/www/us/en/programmable/support/literature/lit-dp.html#stratix-10